industrial temperature range idt74alvch32501 3.3v cmos 36-bit universal bus transceiver with 3-state outputs 1 december 2002 industrial temperature range the idt logo is a registered trademark of integrated device technology, inc. ?2002 integrated device technology, inc. dsc-4764/3 features: ? 0.5 micron cmos technology ? typical t sk(o) (output skew) < 250ps ? esd > 2000v per mil-std-883, method 3015; > 200v using machine model (c = 200pf, r = 0) ?v cc = 3.3v 0.3v, normal range ?v cc = 2.7v to 3.6v, extended range ?v cc = 2.5v 0.2v ? cmos power levels (0.4 w typ. static) ? rail-to-rail output swing for increased noise margin ? available in 114-ball lfbga package functional block diagram drive features: ? high output drivers: 24ma ? suitable for heavy loads applications: ? 3.3v high speed systems ? 3.3v and lower voltage computing systems idt74alvch32501 3.3v cmos 36-bit universal bus trans- ceiver with 3-state outputs and bus-hold description: this 36-bit universal bus transceiver is built using advanced dual metal cmos technology. the alvch32501 combines d-type latches and dtype flip-flops to allow data flow in transparent latched and clocked modes. data flow in each direction is controlled by output-enable (oeab and oeba ), latch enable (leab and leba), and clock (clkab and clkba) inputs. for a-to-b data flow, the device operates in transparent mode when leab is high. when leab is low, the a data is latched if clkab is held at a high or low logic level. if leab is low, the a bus data is stored in the latch/ flip- flop on the low-to-high transition of clkab. oeab performs the output enable function on the b port. data flow from b port to a port is similar but requires using oeba , leba and clkba. flow-through organization of signal pins simplifies layout. all inputs are designed with hysteresis for improved noise margin. this alvch32501 has been designed with a 24ma output driver. this driver is capable of driving a moderate to heavy load while maintaining speed performance. the alvch32501 has ?bus-hold? which retains the inputs? last state whenever the input goes to a high impedance. this prevents floating inputs and eliminates the need for pull-up/down resistors. to 17 other channels 1 oeab 1 clkba 1 leba 1 oeba 1 clkab 1 leab 1 a 1 d c d c d c d c 1 b 1 a2 a3 a4 j3 k3 j4 b3 a5 to 17 other channels 2 oeab 2 clkba 2 leba 2 oeba 2 clkab 2 leab 2 a 1 d c d c d c d c 2 b 1 l2 k2 k5 v3 w3 v4 l3 l5
industrial temperature range 2 idt74alvch32501 3.3v cmos 36-bit universal bus transceiver with 3-state outputs lfbga topview 114 ball lfbga package attributes pin configuration 1.5mm max. 1.4mm nom. 1.3mm min. 0.8mm top view a b c d e f g h j k l m n p r t u v w 6 5 4 3 2 1 1 2 3 4 5 6 a b c d e f g h j k l m n p r t u v w 16mm 5.5mm abc e f g h j k l m np d t r u w v 6 5 4 3 2 1 1 b 6 1 b 8 1 b 9 1 b 10 1 b 12 1 b 16 gnd 1 b 4 1 b 5 1 b 7 1 b 14 1 b 15 1 b 11 1 b 13 1 b 2 1 b 3 1 b 1 v cc gnd 2 b 6 1 b 17 2 b 7 2 b 9 2 b 8 2 b 3 2 b 10 1 b 18 2 b 12 gnd v cc 1 a 1 gnd v cc 2 oeab 1 a 2 1 a 3 2 a 10 2 a 11 gnd v cc 1 a 10 1 a 12 1 a 4 1 a 51 a 7 1 a 14 1 a 15 2 a 3 2 a 6 2 leab 2 a 1 2 a 8 1 a 18 1 a 6 1 a 8 1 a 9 1 a 16 1 a 11 1 a 13 2 a 2 2 a 4 1 a 17 2 a 5 2 a 7 gnd gnd v cc gnd v cc v cc gnd gnd 1 leba gnd gnd gnd 2 b 5 2 b 4 1 leab gnd 1 clkab 1 clkba 2 b 11 2 b 13 2 b 14 gnd 2 a 12 2 a 9 gnd v cc gnd 1 oeab 1 oeba 2 a 13 2 a 14 2 a 18 2 a 16 2 oeba 2 leba 2 b 16 2 b 15 2 b 18 2 b 17 gnd 2 a 15 2 a 17 gnd 2 clkba 2 clkab 2 b 1 2 b 2 gnd nc nc
industrial temperature range idt74alvch32501 3.3v cmos 36-bit universal bus transceiver with 3-state outputs 3 symbol description max unit v term (2) terminal voltage with respect to gnd ?0.5 to +4.6 v v term (3) terminal voltage with respect to gnd ?0.5 to v cc +0.5 v t stg storage temperature ?65 to +150 c i out dc output current ?50 to +50 ma i ik continuous clamp current, 50 ma v i < 0 or v i > v cc i ok continuous clamp current, v o < 0 ?50 ma i cc continuous current through each 100 ma i ss v cc or gnd absolute maximum ratings (1) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v cc terminals. 3. all terminals except v cc . note: 1. as applicable to the device type. symbol parameter (1) conditions typ. max. unit c in input capacitance v in = 0v 5 7 pf c out output capacitance v out = 0v 7 9 pf c i/o i/o port capacitance v in = 0v 7 9 pf capacitance (t a = +25c, f = 1.0mhz) pin names description oeab a-to-b output enable input oeba b-to-a output enable input (active low) leab a-to-b latch enable input leba b-to-a latch enable input clkab a-to-b clock input clkba b-to-a clock input x a x a-to-b data inputs or b-to-a 3-state outputs (1) x b x b-to-a data inputs or a-to-b 3-state outputs (1) pin description note: 1. these pins have "bus-hold". all other pins are standard inputs, outputs, or i/os. function table (each flip-flop) (1,2) notes: 1. h = high voltage level l = low voltage level x = don?t care z = high impedance = low-to-high transition 2. a-to-b data flow is shown. b-to-a data flow is similar but uses oeba , leba, and clkba. 3. output level before the indicated steady-state conditions were established. 4. output level before the indicated steady-state conditions were established, provided that clkab was high before leab went low. inputs outputs oeab leab clkab xax xbx lx x x z hh x l l hh x h h hl ll hl hh hl l x b (3) hl h x b (4)
industrial temperature range 4 idt74alvch32501 3.3v cmos 36-bit universal bus transceiver with 3-state outputs symbol parameter test conditions min. typ. (1) max. unit v ih input high voltage level v cc = 2.3v to 2.7v 1.7 ? ? v v cc = 2.7v to 3.6v 2 ? ? v il input low voltage level v cc = 2.3v to 2.7v ? ? 0.7 v v cc = 2.7v to 3.6v ? ? 0.8 i ih input high current v cc = 3.6v v i = v cc ?? 5a i il input low current v cc = 3.6v v i = gnd ? ? 5a i ozh high impedance output current v cc = 3.6v v o = v cc ?? 10 a i ozl (3-state output pins) v o = gnd ? ? 10 v ik clamp diode voltage v cc = 2.3v, i in = ?18ma ? ?0.7 ?1.2 v v h input hysteresis v cc = 3.3v ? 100 ? mv i ccl quiescent power supply current v cc = 3.6v ? 0.1 40 a i cch v in = gnd or v cc i ccz ? i cc quiescent power supply current one input at v cc - 0.6v, other inputs at v cc or gnd ? ? 750 a variation dc electrical characteristics over operating range following conditions apply unless otherwise specified: operating condition: t a = ?40c to +85c note: 1. typical values are at v cc = 3.3v, +25c ambient. bus-hold characteristics symbol parameter (1) test conditions min. typ. (2) max. unit i bhh bus-hold input sustain current v cc = 3v v i = 2v ? 75 ? ? a i bhl v i = 0.8v 75 ? ? i bhh bus-hold input sustain current v cc = 2.3v v i = 1.7v ? 45 ? ? a i bhl v i = 0.7v 45 ? ? i bhho bus-hold input overdrive current v cc = 3.6v v i = 0 to 3.6v ? ? 500 a i bhlo notes: 1. pins with bus-hold are identified in the pin description. 2. typical values are at v cc = 3.3v, +25c ambient.
industrial temperature range idt74alvch32501 3.3v cmos 36-bit universal bus transceiver with 3-state outputs 5 operating characteristics, t a = 25c v cc = 2.5v 0.2v v cc = 3.3v 0.3v symbol parameter test conditions typical typical unit c pd power dissipation capacitance outputs enabled c l = 0pf, f = 10mhz 88 108 pf c pd power dissipation capacitance outputs disabled 12 12 note: 1. v ih and v il must be within the min. or max. range shown in the dc electrical characteristics over operating range table for the appropriat e v cc range. t a = ? 40c to + 85c. output drive characteristics symbol parameter test conditions (1) min. max. unit v oh output high voltage v cc = 2.3v to 3.6v i oh = ? 0.1ma v cc ? 0.2 ? v v cc = 2.3v i oh = ? 6ma 2 ? v cc = 2.3v i oh = ? 12ma 1.7 ? v cc = 2.7v 2.2 ? v cc = 3v 2.4 ? v cc = 3v i oh = ? 24ma 2 ? v ol output low voltage v cc = 2.3v to 3.6v i ol = 0.1ma ? 0.2 v v cc = 2.3v i ol = 6ma ? 0.4 i ol = 12ma ? 0.7 v cc = 2.7v i ol = 12ma ? 0.4 v cc = 3v i ol = 24ma ? 0.55
industrial temperature range 6 idt74alvch32501 3.3v cmos 36-bit universal bus transceiver with 3-state outputs switching characteristics (1) v cc = 2.5v 0.2v v cc = 2.7v v cc = 3.3v 0.3v symbol parameter min. max. min. max. min. max. unit t plh propagation delay 1 5.3 ? 4.9 1 4.2 ns t phl xclk to xqx t plh propagation delay 1 4.8 ? 4.5 1 3.9 ns t phl xax to xbx or xbx to xax t plh propagation delay 1.1 5.7 ? 5.3 1.3 4.6 ns t phl le to xax or xbx t plh propagation delay 1.2 6.1 ? 5.6 1.4 4.9 ns t phl clk to ax or bx t pzh output enable time 1.3 6.3 ? 6 1.1 5 ns t pzl oeba to xax t pzh output enable time 1 5.8 ? 5.3 1 4.6 ns t pzl oeab to xbx t phz output disable time 1.3 5.3 ? 4.6 1.3 4.2 ns t plz oeba to xax t phz output disable time 1.5 6.2 ? 5.7 1.4 5 ns t plz oeab to xbx t su set-up time, data before clk 2.2 ? 2.1 ? 1.7 ? ns t h hold time, data after clk 0.6 ? 0.6 ? 0.7 ? ns t su set-up time, data before le clk high 1.9 ? 1.6 ? 1.5 ? ns clk low 1.3 ? 1.1 ? 1 ? t h hold time, data after le , clk high or low 1.4 ? 1.7 ? 1.4 ? ns t w pulse width,le high 3.3 ? 3.3 ? 3.3 ? ns t w pulse width, clk high or low 3.3 ? 3.3 ? 3.3 ? ns t sk (o) output skew (2) ? ? ? ? ? 500 ps notes: 1. see test circuits and waveforms. t a = ? 40c to + 85c. 2. skew between any two outputs of the same package and switching in the same direction.
industrial temperature range idt74alvch32501 3.3v cmos 36-bit universal bus transceiver with 3-state outputs 7 open v load gnd v cc pulse generator d.u.t. 500 ? 500 ? c l r t v in v out (1, 2) alvc link input v ih 0v v oh v ol t plh1 t sk (x) output 1 output 2 t phl1 t sk (x) t plh2 t phl2 v t v t v oh v t v ol t sk (x) = t plh2 - t plh1 or t phl2 - t phl1 alvc link same phase input transition opposite phase input transition 0v 0v v oh v ol t plh t phl t phl t plh output v ih v t v t v ih v t alvc link data input 0v 0v 0v 0v t rem timing input synchronous control t su t h t su t h v ih v t v ih v t v ih v t v ih v t alvc link asynchronous control low-high-low pulse high-low-high pulse v t t w v t alvc link control input t plz 0v output normally low t pzh 0v switch closed output normally high enable disable switch open t phz 0v v lz v oh v t v t t pzl v load/2 v load/2 v ih v t v ol v hz alvc link test circuits and waveforms propagation delay test circuit for all outputs enable and disable times set-up, hold, and release times notes: 1. for t sk (o) output1 and output2 are any two outputs. 2. for t sk (b) output1 and output2 are in the same bank. definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator. notes: 1. pulse generator for all pulses: rate 1.0mhz; t f 2.5ns; t r 2.5ns. 2. pulse generator for all pulses: rate 1.0mhz; t f 2ns; t r 2ns. output skew - t sk ( x ) pulse width note: 1. diagram shown for input control enable-low and input control disable-high. symbol v cc (1) = 3.3v0.3v v cc (1) = 2.7v v cc (2) = 2.5v0.2v unit v load 6 6 2 x vcc v v ih 2.7 2.7 vcc v v t 1.5 1.5 vcc / 2 v v lz 300 300 150 mv v hz 300 300 150 mv c l 50 50 30 pf test conditions switch position test switch open drain disable low v load enable low disable high gnd enable high all other tests open
industrial temperature range 8 idt74alvch32501 3.3v cmos 36-bit universal bus transceiver with 3-state outputs ordering information corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 logichelp@idt.com santa clara, ca 95054 fax: 408-492-8674 (408) 654-6459 www.idt.com idt xx alvc xxxx xx package device type temp. range bf bfg 32 74 low-profile fine pitch ball grid array lfbga - green 36-bit universal bus transceiver with 3-state outputs -40c to +85c xxx family bus-hold 501 bus-hold 32-bit bus density, 24ma h
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